The present invention relates to a technique for fabricating a compound semiconductor device using a silicon (Si) single crystal substrate having a specific azimuth with respect to the plane of the substrate.
As one of Group III-V compound semiconductors, a boron phosphide (BP)-base Group Ill-V compound semiconductor (boron phosphide-base semiconductor) containing boron (B) and phosphorus (P) as constituent elements is known (see, Iwao Teramoto, Handotai Device Gairon (Introduction of Semiconductor Device), 1st ed., pp. 26-28, Baifukan (Mar. 30, 1995)). The boron phosphide (BP) has a small Philips ionicity of 0.006 (see, Philips, Handotai Ketsugo Ron (Bonds and Bands in Semiconductors), 3rd imp., page 51, Yoshioka Shoten (Jul. 25, 1985)) and is a substance almost comprising a covalent bond. Furthermore, this is a zinc-blende type cubic crystal and therefore, has a band structure of degenerate valence band (see, Toshiaki Ikoma and Hideaki Ikoma, Kagobutsu Handotai no Kiso Bussei Nyumon (Guide for Basic Physical Properties of Compound Semiconductor), 1st ed., pp. 14-17, Baifukan (Sep. 10, 1991)). By virtue of this, boron phosphide is advantageous in that a p-type electrically conducting layer can be readily formed.
Conventionally, various compound semiconductor devices are fabricated by using a boron phosphide layer provided on a silicon (Si) single crystal substrate. For example, a hetero-bipolar transistor (HBT) using a boron phosphide layer is known (see, J. Electrochem. Soc., 125(4), pp. 633-637 (1978)). Also, a solar cell using a boron phosphide layer as the window layer is known (see, J. Electrochem. Soc., supra). Furthermore, techniques for fabricating a blue-band or green-band light emission diode (LED) or laser diode (LD) using boron phosphide and a mixed crystal thereof are disclosed (see, Japanese Patents (1) 2809690, (2) 2809691 and (3) 2809692, and (4) U.S. Pat. No. 6,069,021).
The lattice constant of a monomer boron phosphide (BP, boron monosphosphide) is about 4.538 xc3x85 (see, Handotai Device Gairon (Introduction of Semiconductor Device), supra, page 28). On the other hand, the silicon (Si) single crystal used as the substrate is also a zinc-blende type cubic crystal and the lattice constant thereof is about 5.431 xc3x85 (see, Handotai Device Gairon (Introduction of Semiconductor Device), supra, page 28). Accordingly, the lattice mismatch degree expressed by the ratio of difference (=0.893 xc3x85) in the lattice constant of both crystals to the lattice constant (=5.431 xc3x85) of silicon single crystal is as large as about 16.6%. In order to prevent peeling of the boron phosphide layer from the Si substrate surface due to this large lattice mismatch degree, technical means of providing a low-temperature buffer layer on the Si substrate surface is disclosed, where the buffer layer comprises a polycrystalline boron phosphide containing an amorphous portion grown at a relatively low temperature (see, U.S. Pat. No. 6,069,021, supra).
In conventional techniques, the boron phosphide-base semiconductor layer is formed using, for example, a silicon single crystal having a surface of {100} or {111} crystal plane as the substrate (see, U.S. Pat. No. 6,069,021, supra). In particular, silicon atoms are densely present on the {111} crystal plane as compared with {100} crystal plane and this is considered effective for preventing boron (B) and phosphorus (P) constituting the low-temperature buffer layer from penetrating into the inside of the silicon single crystal substrate.
However, the distance between {111} crystal planes of the silicon single crystal is about 3.136 xc3x85, whereas the distance of {110} crystal planes of boron phosphide (BP, lattice constant=4.538 xc3x85) is 3.209 xc3x85 and does not agree with the distance between {111} crystal planes of the silicon single crystal. Therefore, the boron phosphide layer provided on a conventional silicon single crystal substrate having a surface of {111} crystal plane is disadvantageously a poor-quality crystal layer containing a large amount of crystal defects such as dislocation or stacking fault.
The present invention provides a technique for giving a boron phosphide-base semiconductor layer having excellent crystallinity by using a silicon single crystal substrate having a surface such that the distance between {111} crystal planes of silicon intersecting with the surface of {111} silicon single crystal agrees with the distance between {110} crystal planes of boron phosphide.
The object of the present invention is to solve the above-described problems in conventional techniques by specifying the azimuth of the crystal plane constituting the surface of a silicon single crystal substrate. More specifically, the present invention provides the following embodiments:
(1) a compound semiconductor device comprising a silicon (Si) single crystal substrate having provided on the surface thereof a boron phosphide (BP)-base semiconductor layer containing boron (B) and phosphorus (P) as constituent elements, wherein the surface of the silicon single crystal substrate is a {111} crystal plane inclined at an angle of 5.0xc2x0 to 9.0xc2x0 toward the  less than 110 greater than  crystal azimuth;
(2) the compound semiconductor device as describe in (1) above, wherein the surface of the silicon single crystal substrate is a {111} crystal plane inclined at an angle of 7.3xc2x10.5xc2x0 toward the  less than 110 greater than  crystal azimuth;
(3) the compound semiconductor device as described in (1) above, which comprises a stacked layer structure such that a boron phosphide-base semiconductor layer having a {110} crystal plane is stacked on a silicon single crystal substrate having a surface of {111} crystal plane inclined at an angle of 5.0xc2x0 to 9.0xc2x0 toward the  less than 110 greater than  crystal azimuth, through a low-temperature buffer layer composed of a boron phosphide-base semiconductor layer;
(4) the compound semiconductor device as described in (2) above, which comprises a stacked layer structure such that a boron phosphide (BP) semiconductor layer having a {110} crystal plane is stacked on a silicon single crystal substrate having a surface of {111} crystal plane inclined at an angle of 7.3xc2x10.5xc2x0 toward the  less than 110 greater than  crystal azimuth, through a low-temperature buffer layer composed of a boron phosphide-base semiconductor layer;
(5) a light-emitting device comprising the compound semiconductor device described in any one of (1) to (4) above; and
(6) a transistor comprising the compound semiconductor device described in any one of (1) to (4) above.
Furthermore, the present invention provides the following embodiments:
(7) a method for producing a compound semiconductor device, comprising stacking a boron phosphide-base semiconductor layer having a {110} crystal plane on a silicon single crystal substrate having a surface of {111} crystal plane inclined at an angle of 5.0xc2x0 to 9.0xc2x0 toward the  less than 110 greater than  crystal azimuth, through a low-temperature buffer layer composed of a boron phosphide-base semiconductor layer; and
(8) a method for producing a compound semiconductor device, comprising stacking a boron phosphide (BP) semiconductor layer having a {110} crystal plane on a silicon single crystal substrate having a surface of {111} crystal plane inclined at an angle of 7.3xc2x10.5xc2x0 toward the  less than 110 greater than  crystal azimuth, through a low-temperature buffer layer composed of a boron phosphide-base semiconductor layer.